1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a data output circuit of a semiconductor memory device and an operation method thereof.
2. Discussion of Related Art
In general, a semiconductor memory device includes a data output circuit that amplifies data read from a core circuit having memory cells and outputs the amplified data to the outside in a read operation. The construction and operation of the data output circuit will be described in more detail below with reference to FIG. 1.
FIG. 1 is a schematic block diagram of a data output circuit and memory banks of a semiconductor memory device in the related art.
Referring to FIG. 1, a data output circuit 10 includes Input and Output (IO) sense amplifier units AM1 to AMK (K is an integer), a multiplexer circuit unit 11, a pipeline latch unit 12, and an output driver circuit unit 13.
Each of the I/O sense amplifier units AM1 to AMK includes sense amplifiers A1 to A32 respectively connected between local I/O lines LIO1 to LIO32 and global I/O lines GIO1 to GIO32 of each of memory banks MB1 to MBK.
The multiplexer circuit unit 11 includes multiplexers MX1 to MX16. Each of the multiplexers MX1 to MX16 is connected to two global I/O lines. For example, the multiplexer MX1 may be connected to the global I/O lines GIO1, GIO32 and the multiplexer MX2 may be connected to the global I/O lines GIO2, GIO31. Furthermore, the multiplexer MX16 is connected to the global I/O lines GIO16, GIO17.
The multiplexers MX1 to MX16 select data received from one of the two global I/O lines connected thereto in response to a control address signal XADD. For example, the multiplexer MX1 may output data received through one of the global I/O lines GIO1, GIO32 in response to the control address signal XADD.
The pipeline latch unit 12 includes latch circuits PLT1 to PLT32. The latch circuits PLT1 to PLT16 latch read data RDO1 to RDO16 respectively received from the multiplexers MX1 to MX16 in response to latch signals LC1 to LC16, respectively, and output latched data. The latch circuits PLT17 to PLT32 latch data respectively received from the global I/O lines GIO17 to GIO32 in response to the latch signals LC17 to LC32, respectively, and output latched data.
The output driver circuit unit 13 includes output drivers DRV1 to DRV32. The output drivers DRV1 to DRV32 output output data ODAT1 to ODAT32, respectively, in response to the read data RDO1 to RDO32 respectively received from the latch circuits PLT1 to PLT32.
An output data width of the semiconductor memory device including the data output circuit 10 is X16 or X32 and can be selectively changed. That is, the data output circuit 10 has the function of changing the output data width.
In more detail, the data output circuit 10 employs only the output drivers DRV1 to DRV16 and outputs 16-bit data when the output data width is set to X16, and outputs 32-bit data employing the whole output drivers DRV1 to DRV32 when the output data width is set to X32.
Meanwhile, when the output data width of the semiconductor memory device is set to X16, the multiplexers MX1 to MX16 must select read data loaded on the global I/O lines GIO1 to GIO16 or must select read data loaded on the global I/O lines GIO17 to GIO32. A row address signal may be used as a signal to control the operation of selecting the multiplexers MX1 to MX16.
In general, the row address signal for controlling the operation of selecting the multiplexers MX1 to MX16 is input once when an active command is input to the semiconductor memory device, but is not input when a read command is input to the semiconductor memory device. Therefore, when the active command is input to the semiconductor memory device, the multiplexers MX1 to MX16 select the read data loaded on the global I/O lines GIO to GIO16 or GIO17 to GIO32 according to the row address signal and output the selected data.
However, in the case where the data stored in the memory banks MB1, MBK are sequentially read with plural ones (for example, MB1, MBK) of the memory banks MB1 to MBK being active, there is a problem in which the multiplexers MX1 to MX16 may select erroneous read data, resulting in failure in the read operation.
In more detail, there may be cases in which the data output circuit 10 must output the read data loaded on the local I/O lines LIO1 to LIO16 to the memory bank MB1 and the data output circuit 10 must output the read data loaded on the local I/O lines LIO17 to LIO32 to the memory bank MBK. In this case, in the event that the multiplexers MX1 to MX16 are set to select the read data loaded on the global I/O lines GIO1 to GIO16 according to the row address signal input along with the active command, the read operation of the memory bank MB1 may be normally performed, but the read operation of the memory bank MBK cannot be normally performed.
As described above, in the data output circuit 10, when the output data width is X16, the multiplexers MX1 to MX16 select the read data respectively loaded on some (GIO1 to GIO16 or GIO17 to GIO32) of the global I/O lines GIO1 to GIO32 and output selected data. Accordingly, when the read operations of the plurality of memory banks are sequentially executed, a problem arises because failure occurs in the read operation.